This invention relates to a bipolar device and more particularly to a method of manufacturing an integrated injection logic device (referred to as "I.sup.2 L" hereinafter).
It is well known that IC's are categorized into bipolar devices and MOS devices and both cover different ranges of applications dependent upon the respective inherent features. It is much more difficult to incorporate bipolar devices onto LSI chips than for MOS devices because of its complexity in construction.
However, the recent development of I.sup.2 L devices provides bipolar devices with access to large scale circuit integration. The I.sup.2 L device is a gate circuit composed of complementary transistors. As shown by FIG. 1 of a basic circuit diagram, a pnp transistor serves as a source of current and a load while an npn transistor serves as an inverter and has multi-collector outputs.
To complete the manufacture of the I.sup.2 L device, an N-type epitaxial layer is first deposited over an N.sup.+ substrate or an N.sup.+ buried layer. A P-type impurity is then diffused into a region corresponding to the base of the inverter transistor and a region corresponding to the emitter of the injector pnp transistor. N.sup.+ diffusion corresponding to the multi-collector of the inverter is effected within the base region. Subsequently, a surface isolation is removed and internal connections are provided for attachment of electrodes.
Nevertheless, the performance of the resulting I.sup.2 L device is not good while not only the construction but also the manufacture procedure are considerably simplified. N.sup.+ collar diffusion which surrounds the base region is needed to meet performance requirements resulting in a one-step increase in the diffusion and masking process.
Attempts have been made to effect the above-mentioned N.sup.+ collar diffusion and the N.sup.+ multi-collector diffusion at the same time. In this case, an increase in the mask registration step and the diffusion step is avoided. However, it is not expected that the upward current gain is increased because of provision of the collar.
For example, in case of an I.sup.2 L device having an N.sup.+ collector but not an N.sup.+ collar diffusion layer, a ratio of upward current gain Bu to downward current gain Bf is depicted by the curve (1) in FIG. 2. In the case where the N.sup.+ collector diffusion and the N.sup.+ collar diffusion are effected independently of each other, the gain ratio is represented by the curve (2). Curve (3) shows the gain ratio of the device where the N.sup.+ collector and the N.sup.+ collar are simultaneously formed. In other words, the deeper the diffusion of the collector (the higher Bf), the greater the advantage of the collar, followed by an increase in the upward current gain Bu. However, the curve (3) in FIG. 2 does not conform to the curve (2) and thus, does not achieve the performance of curve (2).
According to a preferred method of the present invention, the above-discussed relationship is improved as shown by the curve (4) to approach the performance of the curve (2). Higher downward current gain Bf is needed to obtain a given upward current gain Bu.
For example, when it is desired to obtain Bu beyond the line B of FIG. 2, the curve (1) needs the highest value of Bf for the curves (3), (4) and (2), respectively. As stated briefly, the diffusion process of the present invention results in the curve (4) which substantially conforms to the curve (2) on the line B. Since no emitter-to-collector breakdown voltage is reduced when the upward current gain is high, it is required that the breakdown voltage be above a power supply voltage.